1. Field of the Invention
The present invention relates to a method for forming a multi-layer metal line of a semiconductor device, and in particular to an improved method for forming a multi-layer metal line of a semiconductor device wherein an insulating film having a low dielectric constant is used in a formation process of an interlayer insulating film of the multi-layer metal line to improve characteristics and reliability of the device.
2. Description of the Background Art
In general, a line of a semiconductor device for electrically connecting devices or device to an external circuit is formed by filling a contact hole and a via hole for interconnection with a line material to form a line layer, and performing subsequent processes. In particular, a metal line is used in a region where a low resistance is required.
The metal line is formed by filling the contact hole and the via hole with the line material, such as an aluminum alloy containing aluminum and a small amount of silicon and/or copper which has a low resistance and excellent processing characteristics according to sputtering of physical vapor deposition (PVD).
Due to a high integration tendency of the semiconductor device, in a process formation of a metal line, a low-K material layer having a low dielectric constant is formed as an interlayer insulating material to reduce resistance capacitance delay by spin coating, and a via hole for connecting an upper line to a lower line is formed, and filled the via hole to form a tungsten contact plug.
Here, since the insulating film is non-uniformly coated on the metal line by the spin-coating process, the thickness of the insulating film depends on a width and density of the metal line therebelow.
An inter-capacitance value between the upper metal line and the lower metal line varies due to non-uniform thickness according to the width and density of the metal line, which deteriorates characteristics of the device.
Moreover, bowing phenomenon occurs during a dry etching process of the via hole, which complicates etching conditions, and the bowing on the sidewalls of the via hole makes deposition of an adhesive film and a diffusion barrier film difficult, which complicates a subsequent process, namely a formation process of a tungsten contact plug.
Furthermore, the end of the metal line is shorted and rounded due to a proximate effect during the patterning process of the metal line, which reduces process margin in a via contact etching process. As a result, the characteristics of the device are deteriorated.
FIGS. 1a to 1e are cross-sectional views illustrating a conventional method for forming a multi-layer metal line of a semiconductor device.
Referring to FIG. 1a, a lower metal line 13 is formed on a semiconductor substrate 11. Here, the lower metal line 13 is composed of an aluminum alloy, and has Ti or Ti/TiN stacked layer at the upper and lower portions of the lower metal line 13.
Reference numeral 100 denotes a region where the area of the lower metal line varies, and reference numeral 200 denotes a region where the density of the lower metal line varies. That is, a metal line having a large area is formed at the left side of region 100, and a metal line having a small area is formed at the right side thereof. A density of the metal line at the left side of the region 200 is relatively higher than that of the right side thereof.
Thereafter, an insulating film 15 having a low dielectric constant is formed on the entire surface. Here, the insulating film 15 is formed according to spin coating using a material having a dielectric constant of about 3.
Although the insulating film 15 has an excellent filling property between metals, namely high step coverage, it is not uniformly coated on the metal line due to its adhesiveness, but unevenly coated on the metal line depending on a width and density of the metal line.
In general, the insulating film 15 is coated thicker on the metal line having the larger area than on the metal line having the smaller area, and in the region having high metal line density than the region having low metal line density.
Thereafter, an oxide film 17 is deposited on the insulating film 15 according to plasma enhanced chemical vapor deposition (PECVD).
Here, the oxide film 17 is formed using a material having a dielectric constant of about 4 at a thickness ranging from 5000 to 12000 xc3x85.
A chemical mechanical polishing (CMP) is performed on the oxide film 17 to form an interlayer insulating film having a stacked structure of the insulating film 15 and the oxide film 17.
As shown in FIG. 1b, a photosensitive film pattern 19 is formed on the interlayer insulating films 15 and 17.
Here, the photosensitive film pattern 19 is formed according to exposure and development processes using a via contact mask (not shown).
As illustrated in FIG. 1c, a via contact hole 21 exposing the lower metal line 13 is formed by etching the interlayer insulating films 17 and 15 using the photosensitive film pattern 19 as a mask.
Since an etch selectivity ratio of the insulating film 15 is at least 1.5 times higher than the etch selectivity ratio of the oxide film 17, the insulating film 15 which is thicker is laterally etched.
The residual photosensitive film pattern 19 is removed after the etching process, and a Ti/TiN film 23 which is an adhesive layer/diffusion barrier film is formed on the entire surface of the resulting structure including the via contact hole 21.
As depicted in FIG. 1d, a tungsten layer 25 for contact plug is formed on the entire surface of the resulting structure according to the PECVD to contact the lower metal line 13 through the via contact hole 21.
Here, bowing is generated in the laterally-etched portion of the insulating film 15 as shown in @.
As described above, in the conventional method for forming the multi-layer metal line of the semiconductor device a bowing phenomenon in the subsequent process because the insulating film having the high etch selectivity ratio is laterally etched during the via contact etching process, thereby deteriorating the property and reliability of the device.
Accordingly, it is an object of the present invention to provide a method for forming a multi-layer metal line of a semiconductor device which can easily form the sufficient multi-layer metal line for high integration of the semiconductor device by forming a presumed via contact plug without generating bowing.
In order to achieve the above-described object of the invention, there is provided a method for forming a multi-layer metal line of a semiconductor device, including the steps of: (a) forming a first insulating film having a low dielectric constant on a semiconductor substrate having a lower metal line thereon; (b) forming and planarizing a first oxide film on the first insulating film; (c) etching back the first oxide film and the first insulating film until a predetermined thickness of first insulating film remains on the lower metal line; (d) forming and planarizing a second insulating film having a low dielectric constant on the entire surface of the resulting structure; (e) forming a second oxide film on the second insulating film; (f) selectively etching the second oxide film and the first and the second insulating films to form a via contact hole exposing the lower metal line; (g) forming an adhesive film/diffusion harrier film on the entire surface of the resulting structure; and (i) forming a contact plug filling the via contact hole, and forming an upper metal line contacting the contact plug.
On the other hand, the principle of the present invention will now be explained.
An insulating film having a low dielectric constant is coated, an oxide film is deposited low thereon and then planarized according to CMP, an etch back process is performed thereon by using an etch speed difference, a thickness of the insulating film non-uniformly formed on the metal line according to a width and density of the metal line is minimized, an insulating film having a low dielectric constant is re-formed according to spin coating, and a thin oxide film is formed thereon, thereby maintaining a constant thickness of the insulating film on the metal line, and maintaining a small thickness of oxide film on the interlayer insulating film including the insulating film (dielectric constant. approx. 0.3) and the oxide film (dielectric constant. approx. 0.4). Accordingly, a thickness of the relatively-planarized insulating film is increased so that an inter-capacitance between the upper metal line and the lower metal line can be constantly maintained lower than the existing interlayer insulating film regardless of the width and density of the lower metal line.
In addition, the thickness in the insulating film is constant in a plasma dry etching process for forming a via contact hole, which is advantageous in etching condition setup, and bowing is prevented by applying a condition for forming a polymer on the sidewalls of the via contact hole to the insulating film etching condition, thereby easily forming a tungsten contact plug.
That is, the bowing is prevented by forming the interlayer insulating film including the insulating film and the oxide film mostly with the insulating film, forming the oxide film on the surface thereof, and performing the via contact etching process on the resulting structure, thereby stabilizing the subsequent via contact process.